1. Field of the Invention
The present invention relates to nonvolatile semiconductor memory devices and in particular to a read operation test for nonvolatile semiconductor memory devices.
2. Description of Related Art
As an electrically erasable/programmable nonvolatile semiconductor memory device, flash memories and charge trapping memories are known. In such a nonvolatile semiconductor memory device, a transistor having a charge storage layer is used as a memory cell. When an electron is injected into a charge storage layer, the threshold voltage of the memory cell transistor is increased. When an electron is extracted from a charge storage layer, the threshold voltage of the memory cell transistor is reduced. The magnitude of this threshold voltage is correlated with stored data “1” or “0.”
At the time of data readout, a predetermined read voltage is applied to the gate of the memory cell transistor. The memory cell transistor whose threshold voltage is low (hereafter, referred to as “ON cell”) is turned on and a cell current (ON cell current) flows. Meanwhile, the memory cell transistor whose threshold voltage is high (hereafter, referred to as “OFF cell”) is turned off and a cell current hardly flows. Whether a memory cell transistor is an ON cell or an OFF cell, that is, stored data can be determined by comparing the cell current with a predetermined reference current using a sense amplifier.
Rewriting (writing, erasing) of data is carried out by injecting an electron into a charge storage layer or extracting an electron therefrom. However, as rewriting of data is repeated, a memory cell transistor is deteriorated and its ON cell current is reduced. For this reason, there is a possibility that normal data readout at a maximum guaranteed frequency is impossible in the stage of practical use thought it is possible immediately after manufacture.
To prevent this problem, a “read operation test” is conducted before product shipment. Specifically, it is determined whether or not data can be accurately read at a maximum guaranteed frequency even after a memory cell transistor is deteriorated. When data is accurately read, the test result is PASS and the product is judged “non-defective.” When data is not accurately read, the test result is FAIL and the product is judged “defective.” This read operation test is also designated as “read speed margin judgment test.”
One of techniques for implementing a read operation test with cell deterioration taken into account is to simulatedly bring the memory cell transistors in products into a state after deterioration. Specifically, the threshold voltage of a memory cell transistor is adjusted so that the ON cell current of the memory cell transistor is brought to a predetermined level (level after cell deterioration). For this purpose, short-time writing or erasing is carried out on the memory cell transistor. However, the writing time or the erasing time it takes for the ON cell current to reach the predetermined level varies from memory cell transistor to memory cell transistor because of production tolerance or the like. For this reason, it is necessary to repeat short-time writing or erasing a large number of times while checking the ON cell current point by point. This incurs increase in test time and manufacturing cost.
Japanese Patent Application Publication No. 2003-331599 describes a technique for shortening a time required for read operation tests. Description will be given to the technique described in Japanese Patent Application Publication No. 2003-331599 with reference to FIG. 1.
Each memory cell transistor is coupled to a sense amplifier through a bit line and a Y selector. Further, each bit line is coupled with a current mirror circuit. This current mirror circuit is provided to “simulatedly” pass an ON cell current after deterioration through each bit line. More detailed description will be given. When test voltage is applied to an external terminal PAD, a simulated ON cell current Iond is produced in the current mirror circuit. The magnitude of ON cell current of the deteriorated memory cell is measured beforehand and the test voltage is set so that the simulated ON cell current Iond becomes equal to the ON cell current of the deteriorated memory cell.
In a read operation test, all the memory cell transistors are turned off and the above test voltage is applied to the external terminal PAD. As a result, the simulated ON cell current Iond is passed through each bit line. The sense amplifier compares the simulated ON cell current Iond with a reference current and outputs data corresponding to the result of the comparison. A read operation test with cell deterioration taken into account can be carried out by passing a simulated ON cell current Iond using a current mirror circuit as mentioned above. Since it is unnecessary to actually establish a deteriorated state, a test time is shortened.